1. Field of the Invention
The present invention relates to nanodots formed on silicon oxide and a method of manufacturing the same. More particularly, the present invention relates to nanodots whose location can be controlled so that the nanodots are regularly arranged on the silicon oxide.
2. Description of the Related Art
Nanodots may be used in a wide variety of optical devices including, e.g., light emitting diodes (LEDs), laser diodes (LDs) and photodetectors. Nanodots may also be used in, e.g., single electron transistors, etc. Though the use of nanodots, it may be possible improve the performance of a device by, e.g., reducing a threshold current of the device, improving retention characteristics, increasing an optical gain, etc.
As an example, when a plurality of nanodots are distributed throughout a floating gate of a flash memory device, the current required for storing information may be smaller than the current required for a conventional flash memory device having no nanodots, and, thus, the amount of power consumed may be decreased by using the nanodot device. The improved characteristics exhibited by the nanodot device may be attributed to Coulomb blockage at room temperature when nanodots smaller than about 10 nm in diameter are used for a floating gate, with the result that a threshold voltage shift may be quantized and multi-bit information may be stored. Accordingly, nanodot technology is considered promising for next-generation technology.
Conventional methods for forming nanodots typically utilize ion implantation to form nanodots on a sample, or rely on adjusting simple process conditions, e.g., deposition temperature, pressure, etc. Accordingly, using conventional methods, it may be difficult to form nanodots having a uniform size and distribution.
FIGS. 1A and 1B illustrate a conventional method of forming germanium (Ge) nanodots on silicon (Si) using a high nuclear generation density at a point where local stress is applied. Referring to FIG. 1A, first Ge nanodots 12a are formed on a silicon substrate 11a. The size and arrangement of the first Ge nanodots 12a tend to be nonuniform. In order to ameliorate the nonuniformity of size, referring to FIG. 1B, silicon 11b may be coated on the first Ge nanodots 12a. The surface of the deposited silicon 11b may be planar. However, the surface stress of the deposited silicon 11b is affected by the first Ge nanodots 12a formed below the deposited silicon 11b. After deposition of silicon 11b, second Ge nanodots 12b are formed on the silicon 11b. The location of the second Ge nanodots 12b may be affected by the location of the first Ge nanodots 12a. For example, the location of the second Ge nanodots 12b may correspond to the region where two Ge first nanodots 12a are adjacent to each other, which may be a result of formation of the first Ge nanodots 12a on a region where surface stress is at a minimum. Thus, the second Ge nanodots 12b may be formed between the two first Ge nanodots 12a. When depositions of silicon and Ge nanodots are repeated according to the above-described principle, Ge nanodots having a uniform size and distribution may be formed, as shown in FIG. 1B.
Another conventional method of forming nanodots (not illustrated) relies on the use of a dislocation network to form nanodots exhibiting uniform size and distribution. According to this method, a dislocation network, which has a regular distribution of dislocations, is initially formed on a substrate. A material is subsequently deposited on the substrate, upon which atoms of the material may move to a location related to the dislocation. These atoms may then crystallize, so that a nanodot array having a regular distribution is formed. In order to form the dislocation network using the above method, preprocessing should be performed so that a coherency strain is applied to the substrate before the nanodots are formed.
When an atomic layer composed of a metal, e.g., gallium (Ga), indium (In), titanium (Ti), aluminum (Al), etc., is formed on a silicon substrate using a method similar to the above-described dislocation network method, the deposition temperature of the atomic layer and thermal processing temperature must be properly adjusted in order to form metal nanodots having a regular arrangement. This allows atoms arranged according to a potential difference at a stacking fault on the surface of the silicon to move to an energetically stable location of the silicon, and subsequently crystallize to from metal nanodots having a regular arrangement.
In the above-described methods of forming nanodots having a regular arrangement, nanodots are formed on a substrate on which preprocessing has been performed to provide regularity. However, it is desirable to form a semiconductor device without such preprocessing. In particular, there is a need for a method of forming nanodots on a surface or layer having no regularity, e.g., a silicon oxide (SiO2) layer.
Conventional methods do not allow for forming nanodots having uniform sizes equal to or smaller than 10 nanometers (nm) on a silicon oxide layer in a uniform array. That is, conventional methods of forming nanodots on a silicon oxide layer rely on adjusting the internal stress of the silicon oxide layer in order to drive an initial nuclear generation density, or rely on adjusting the density of a surface silanol group (Si—OH). Such methods may allow nanodots having a high density to be manufactured. However, since it may be difficult to adjust the size of the nanodots and/or to control the locations thereof, the methods may not be easily adapted to the practical manufacture semiconductor devices. Accordingly, there is a need for a method of manufacturing nanodots in which the size of nanodots is controlled and nanodots are regularly arranged.